My public notebook

Let’s take writing to an external SRAM as an example. The data is written into the SRAM at the rising edge of the “wr” signal, and you need to make sure that the “data” signal is stable during a given time before (the “setup time”) and after (the “hold time”) the rising edge of “wr”.

How do you check that your VHDL module meets the setup and hold time requirements of the SRAM?

Of course, you could just have a look at the waveforms in your VHDL simulation and measure these times using cursors. A better way to do it is to have your VHDL testbench automatically perform these checks for you using two checker processes.

Here’s a simple entity that does just that:

--------------------------------------------------------------------------------
-- Purpose : Checks that the data signal meets the given setup and hold times
--           with respect to the rising edge of the wr signal.
-- Author  : Guy.Eschemann@gmail.com
-- Created : 03-May-2011
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity setup_hold_check is

  generic (
    g_setup_time : time := 5 ns;
    g_hold_time  : time := 10 ns);

  port (
    wr   : in std_logic;
    data : in std_logic_vector(7 downto 0));

end setup_hold_check;

architecture behavioral of setup_hold_check is
begin

  p_check_setup_time : process (wr, data)
  begin
    if rising_edge(wr) then
      assert data'stable(g_setup_time)
        report "Setup time violation" severity error;
    end if;
  end process;

  p_check_hold_time : process (wr'delayed(g_hold_time))
  begin
    if rising_edge(wr'delayed(g_hold_time)) then
      assert data'last_event = 0 ns or data'last_event > g_hold_time
        report "Hold time violation" severity error;
    end if;
  end process;

end behavioral;

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